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| CML Semiconductor Products PRODUCT INFORMATION FX629 Features/Applications Designed to Meet Mil-Std-188-113 Military Communications Delta MUX, Switch and Phone Applications Single-Chip Full-Duplex Codec On-Chip Input and Output Filters DATA ENABLE ENCODER FORCE IDLE Delta Modulation Codec Publication D/629/2 July 1994 Provisional Issue Programmable Sampling Clocks 3 or 4-bit Compand Algorithm Forced Idle Facility Powersave Facility Single 5V CMOS Process Full-Duplex CVSD* Codec ENCODER INPUT VDD V SS XTAL/CLOCK XTAL ENCODER DATA CLOCK DECODER DATA CLOCK VBIAS MODE 1 MODE 2 ALGORITHM POWERSAVE DECODER INPUT DEMOD DECODER OUTPUT DECODER FORCE IDLE CLOCK MODE LOGIC SAMPLING RATE CONTROL MOD ENCODER OUTPUT f1 f0 CLOCK RATE GENERATORS f2 FX629 3 or 4-BIT f3 f1 Fig.1 Internal Block Diagram Brief Description The FX629 is an LSI circuit designed as a *Continuously Variable Slope Delta Codec and is intended for use in military communications systems. Designed to meet Mil-Std-188-113 with external components, the device is suitable for applications in military Delta Multiplexers, switches and phones. Encoder input and decoder output filters are incorporated on-chip. Sampling clock rates can be programmed to 16, 32 or 64 k bits/second from an internal clock generator or may be externally applied in the range 8 to 64 k bits/ second. Sampling clock frequencies are output for the synchronization of external circuits. The encoder has an enable function for use in multiplexer applications. Encoder and Decoder forced idle facilities are provided, forcing a 10101010..... pattern in encode and a VDD/2 bias in decode. The companding circuits may be operated with a pin-selected 3 or 4-bit algorithm. The powersave facility puts the device into the standby mode thereby reducing current consumption when not operating. A reference 1.024MHz oscillator uses an external clock pulse or Xtal input. The FX629 is a low-power, 5 volt CMOS device and is available in 22-pin cerdip DIL package. Pin Number Function FX629J 1 Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally derived clock is injected here. See Clock Mode pins and Figure 3. 2 Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML application note D/XT/1 April 1986. 3 No connection 4 Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see Clock Mode pins). 5 Encoder Output : The encoder digital output, this is a three state output whose condition is set by Data Enable and Powersave inputs as shown : Data Enable 1 0 1 Powersave 1 1 0 Encoder Output Enabled High Z (o/c) Vss 6 Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the encoder encodes as normal. Internal 1M Pullup. 7 Data Enable : Data is made available at the encoder output pin by control of this input. See Encoder Output pin. Internal 1M Pullup. 8 No connection 9 Bias : Normally at VDD /2 bias, this pin requires to be externally decoupled by a capacitor, C4. Internally pulled to V SS when "Powersave" is a logical '0'. 10 Encoder Input : The analogue signal input. Internally biased at V DD /2, external components are required on this input. The source impedance should be less than 100 , output idle channel noise levels will improve with an even lower source impedance. See Fig. 3. 11 VSS : Negative Supply. 2 Pin Number Function FX629J 12 No connection 13 Decoder Output : The recovered analogue signal is output at this pin, it is the buffered output of a bandpass filter and requires external components. During "Powersave" this output is o/c. 14 No connection 15 Powersave : A logical '0' at this pin puts most parts of the codec into a quiescent nonoperational state. When at a logical '1' the codec operates normally. Internal 1M Pullup. 16 Decoder Force Idle : A logical '0' at this pin gates a 0101...pattern internally to the decoder so that the decoder output goes to V DD/2. When this pin is at a logical '1' the decoder operates as normal. Internal 1M Pullup. 17 Decoder Input : The received digital signal input. Internal 1M Pullup. 18 Decoder Data Clock : A Logic I/O port. External decode clock input or internal data clock output, dependant upon clock mode 1, 2 inputs, see Clock Mode pins. 19 Algorithm : A logical '1' at this pin sets this device for a 3-bit companding algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1M Pullup. 20 21 Clock Mode 2 : Clock Mode 1 : Internal 1M Pullups. Clock Mode 1 0 0 1 1 Clock Mode 2 0 1 0 1 Facility External clocks Internal, 64kb/s = f / 16 Internal, 32kb/s = f / 32 Internal, 16kb/s = f / 64 Clock rates refer to f = 1.024 MHz Xtal/clock input. During internal operation the data clock frequencies are available at the ports for external circuit synchronization. Independent or common data rate inputs to Encode and Decode data clock ports may be employed in the External Clocks mode. Optimum performance will be achieved when the applied external clocks are synchronous with the master Xtal/clock, and a sub-multiple of 128kHz. 22 VDD : Positive Supply. A single + 5 volt power supply is required. 3 Codec Integration FX629 PARAMETERS MEASURED HERE REGULATED POWER SUPPLY FX629 PARAMETERS MEASURED HERE SYSTEM INPUT ANALOGUE INPUT INTERFACE (BALUN & BUFFER) FX629 ENCODER FX629 DECODER ANALOGUE OUTPUT INTERFACE (BALUN & BUFFER) SYSTEM OUTPUT DATA CLOCKS CLOCK MODE 16/32/64kb/s DATA CLOCKS 1.024 MHz SYNCHRONOUS CLOCK AND DATA SYSTEM 1.024 MHz Fig.2 System Configuration Diagram - showing the FX629, which with the indicated interfacing, will conform to the Mil-Std-188-113 Specification Component R1 R2 C1 C2 C3 Unit Value 1M Selectable 33p 33p 1.0 Note - with reference to Figure 3 (below) Oscillator Inverter bias resistor. Xtal Drive limiting resistor. Xtal Circuit drain capacitor. Xtal Circuit gate capacitor. Encoder Input coupling capacitor - The drive source impedance to this input should be less than 100. Output Idle channel noise levels will improve with an even lower source impedance. 1.0 Bias decoupling capacitor. C4 C5 1.0 VDD decoupling capacitor. 1.024 MHz A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock X1 rates. Xtal circuitry shown is in accordance with CML application note D/XT/1 April 1986. Tolerance :- Resistors 10% Capacitors 20% VDD XTAL/CLOCK X1 R1 C2 C1 R2 XTAL N/C ENCODER DATA CLOCK ENCODER OUTPUT ENCODER FORCE IDLE DATA ENABLE N/C BIAS ENCODER INPUT C3 C4 VSS 1 2 3 4 5 6 7 8 9 10 11 VDD 22 21 20 19 18 CLOCK MODE 1 CLOCK MODE 2 ALGORITHM DECODER DATA CLOCK DECODER INPUT C5 FX629J 17 DECODER FORCE IDLE 16 POWERSAVE 15 N/C 14 DECODER OUTPUT 13 12 N/C Fig.3 Recommended External Components V SS 4 Codec Timing Information ENCODER TIMING ENCODER CLOCK t DATA CLOCKED CH t IF t CL t CH t IR ENCODER DATA OUTPUT t PCO DECODER TIMING DECODER CLOCK DATA CLOCKED DECODER DATA INPUT t SU MULTIPLEXING FUNCTION ENCODER OUTPUT HIGH Z tH DATA TRUE TIME HIGH Z t DR DATA ENABLE t DF TIMING tCH Clock '1' Pulse Width 1.0s Min. tCL Clock '0' Pulse Width 1.0s Min. tIR Clock Rise Time 100ns Typ. tIF Clock Fall Time 100ns Typ. tDR Data Rise Time 100ns Typ. tSU Data Set-up Time 450ns Min. tH Data Hold Time 600ns Min. tDF Data Fall Time 100ns Typ. tSU + tH = Data True Time tPCO Clock to Output Delay Time 750ns Max. Xtal Input Frequency 1.024MHz. Fig.4 Codec Timing Diagrams Digital to Analogue Performance ...... Using the bit sequence tests shown in Table 1 (below) at the Decoder Input pin, the analogue signals measured at the Decoder Output pin are 800Hz 10Hz at the levels described. Sample Rate Bit Sequence at Decoder Input "Run of Threes" (%) 0 0 Output Level (dBm0) -29.2 2 -30.0 2 01 01 at 800Hz 5 16kbit/s 32kbit/s 11011011010010010010 1101101101010100100100100100101010110110 16kbit/s 32kbits 11111011010000010010 1111110110101010000100000010010101011110 30 30 Table 1 Bit Sequence Tests and Results Typical Codec Performance ...... relative to the Mil-Std-188-113 Specification 3 2 3 2 Attenuation (dB) 1 0 -1 0dBm0 Input Level = 489mVrms -2 -3 - 30 - 20 Input Frequency = 800Hz Ref Level: -15dBm0 = 87mVrms ref. 13 Attenuation (dB) 1 0 -1 -2 -3 0dBm0 Input Level = 489mVrms Input Frequency = 800Hz Ref Level: -15dBm0 = 87mVrms ref. 13 - 10 0 10 - 30 - 20 - 10 0 10 Input Level (dBm0) Fig.5 Gain vs Input Level (16kbit/s) Input Level (dBm0) Fig.6 Gain vs Input Level (32kbit/s) Ref: 0dBm0 Input Level = 489mVrms 20 Input Frequency = 800Hz 25 Ref: 0dBm0 Input Level = 489mVrms Input Frequency = 800Hz S/N Ratio (dB) 10 S/N Ratio (dB) 15 20 5 0 - 30 - 20 - 10 0 15 - 30 - 20 - 10 0 Input Level (dBm0) Input Level (dBm0) Fig.7 S/N vs Input Level (16kbit/s) Fig.8 S/N vs Input Level (32kbit/s) + 10 1.5 0 1.5 - 10 Input Level = -15dBm0 Gain (dB) - 20 - 30 - 40 - 50 ref. - 60 0 0.3 0.8 1 2 2.6 3 4 4.2 5 6 Frequency (kHz) Fig.9 Attenuation Distortion vs Frequency (16kbit/s) 6 Typical Codec Performance ...... relative to the Mil-Std-188-113 Specification 30 Input Level = -15dBm0 20 25 Input Level = -15dBm0 S/N Ratio (dB) S/N Ratio (dB) 15 20 15 10 10 5 5 0 1 2 3 0 1 2 3 3.4 Input Frequency (kHz) Input Frequency (kHz) Fig.10 S/N vs Input Frequency (16kbit/s) Fig.11 S/N vs Input Frequency (32kbit/s) 0 100 90.0 30% 'run-of-threes -6 Amplitude (dB) - 12 - 6dB/octave Amplitude (%) - 18 48.0 Beginning of discharge - 24 10.0 0% 'run-of-threes - 30 10 100 1k 10k 3.0 X X Frequency (Hz) Time (ms) Fig.12 Principal Integrator Response Fig.13 Compand Envelope + 10 3 0 - 10 1 2 Input Level = -15dBm0 Gain (dB) - 20 - 30 - 40 - 50 - 60 0 0.3 1 1.4 2 2.6 3 3.4 4 4.2 5 6 Fig.14 Attenuation Distortion vs Frequency (32kbit/s) 7 Frequency (kHz) Specifications Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage Input voltage at any pin (ref V SS = 0V) Source/sink current (supply pins) (other pins) Total device dissipation @ 25C Derating Operating temperature range: FX629J Storage temperature range: FX629J -0.3 to 7.0V -0.3 to (VDD + 0.3V) 30mA 20mA 800mW Max. 10mW/C -40C to +85C -55C to +125C Operating Limits All characteristics are measured using the following parameters unless otherwise specified: VDD = 5.0V, TAMB = 25C, Xtal/Clock f0 = 1.024MHz, Audio Level 0dB ref (0dBm0) = 489 mV rms. Audio Test Frequency = 800 Hz. Sample Clock Rate = 32kb/s. Compand Algorithm = 3-bit. Characteristics See Note Static Values Supply Voltage 1 Supply Current (Enabled) Supply Current (Powersave) Inputs Logic '1' 8 Inputs Logic '0' 8 Outputs Logic '1' 8 Outputs Logic '0' 8 Digital Input Impedance (Logic I/O pins) Digital Input Impedance (Logic input pins, pullup resistor) 2 Digital Output Impedance Analogue Input Impedance 4 Analogue Output Impedance 7 Three State Output Leakage Current (output disabled) Insertion Loss 3 Dynamic Values 1,9 Encoder: Analogue Signal Input Levels 5,9 Principle Integrator Frequency Encoder Passband Compand Time Constant Decoder: Analogue Signal Output Levels 5,9 Decoder Passband Encoder Decoder (Full codec): Compression Ratio (Cd = 0.3 to Cd = 0.0) Passband Stopband Stopband Attenuation (4200Hz to 6000Hz) (> 6kHz) Passband Gain Passband Ripple (300Hz -1400Hz) (1400Hz - 2600Hz) (2600Hz - 3400Hz) Output Noise (Input short circuit) 9 Perfect Idle Channel Noise (Encoder forced) 9 Group Delay Distortion 6 (1000Hz to 2600Hz) (600Hz to 2800Hz) (500Hz to 3000Hz) Xtal/Clock Frequency Min. 4.5 - - 3.5 - 4.0 - 1.0 300 - - - -4.0 -2.0 -35.0 127 4.0 -35.0 300 - 300 4.2 25.0 - - -1.0 -1.0 -2.0 - - - - - - Typ. 5.0 5.5 0.4 - - - - 10.0 - - 1.0 - - - - 159 3400 5.0 - - 16:1 - - - 60.0 0 - - - -55.0 -57.0 - - - 1024 Max. 5.5 - - - 1.5 - 1.0 - - 4 - 800 +4.0 +2.0 +12.0 212 6.0 +12.0 3400 - 3400 - - - - +1.0 +3.0 +3.0 - - 450 750 1.5 - Unit V mA mA V V V V M k k k A dB dBm0 Hz Hz ms dBm0 Hz Hz kHz dB dB dB dB dB dB dBm0 dBm0 s s ms kHz 8 Specifications ...... Process Information The following Table gives details of the process and test controls employed in the manufacture of the FX629 'Mil Std' Delta Codec. Function Hermeticity Fine Leak Test - Coarse Leak Test - Burnin Temperature Cycling Reference Mil Std 883C Mil Std 883C Mil Std 883C Mil Std 883C Remarks using Method 1014 - test condition A1. using Method 1014 - test condition C. using Method 1015 - test condition E. 168 Hours @ 85C with 5v power, and clocks applied. using Method 1010 - test condition B. 10 cycles -55C to +125C. The following mechanical assembly tests are Qualified to BS9450 Vibration Shock Low Pressure Transport and Storage - Operation - Humidity BS9450 BS9450 BS9450 BS9450 Section 1.2.6.8.1 55Hz to 500Hz at 98 m/sec acceleration. Section 1.2.6.6 981 m/sec for 6 msec. Section 1.2.6.12 225mmHg (altitude 9000m). 600mmHg (altitude 2400m). Section 1.2.6.4 96 Hours @ 45C, 95% relative humidity plus condensed water. Notes: 1. Dynamic characteristics are specified at 5V unless otherwise specified. 2. All logic inputs except, Encoder and Decoder Data Clocks. 3. For an Encoder/Decoder combination, insertion loss contributed by a single component is half this figure. 4. Driven with a source impedance of <100. 5. Recommended values - See Figures 5, 6, 7 and 8. 6 Group Delay Distortion for the full codec is relative to the delay with 820Hz, -20dB at the encoder input. 7. An Emitter Follower output stage. 8. 4.0V = 80% V DD, 3.5V = 70% VDD, 1.5V = 30% VDD, 1.0V = 20% V DD. 9. Analogue Voltage Levels used in this Data Sheet: 0dBm0 = 489mVrms = - 4dBm = 0dB. -15dBm0 = 87mVrms. - 20dBm0 = 49mVrms = - 24dBm. Application Recommendations Due to the very low levels of signal and idle channel noise required in Military applications - a noisy or badly regulated power supply could cause instability putting the overall system performance out of specification. Adherence to the points noted below will assist in minimizing this problem. (a) Care should be taken on the design and layout of the printed circuit board. (b) All external components (as recommended in Figure 3) should be kept close to the package. (c) Tracks should be kept short, particularly the Encoder Input capacitor and the V BIAS capacitor. (d) Xtal/clock tracks should be kept well away from analogue inputs and outputs. (e) Inputs and outputs should be screened wherever possible. (f) A "ground plane" connected to V SS will assist in eliminating external pick-up on the input and output pins. (g) It is recommended that the power supply rails have less than 1mVrms of noise allowed. (h) The source impedance to the Encoder Input pin must be less than 100, Output Idle channel noise levels will improve with even lower source impedances. 9 Package Outlines The FX629 is available in the package style outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. Handling Precautions The FX629 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX629J 22-pin cerdip DIL (J3) NOT TO SCALE Max. Body Length Max. Body Width 27.38mm 9.75mm Ordering Information FX629J 22-pin cerdip DIL (J3) CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. 10 |
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